Magnetic shift register



June '28, 1960 2,943,301

D. LOEV El AL MAGNETIC SHIFT REGISTER Original Filed April 22, 1954 2 Sheets-Sheet 1 A AQVANCE ADVANCE ERASE 2 RESET% 0% E READOUT INVENTORS DAVID LOEV WILLIAM MIEHLE JOSEPH WYLEN ATTORNEY June 28, 1960 Original Filed April D. LO

EV ET AL.

MAGNETIC SHIFT REGISTER 2 Sheets-Sheet 2 B PIC-3.5 9 I o n o READOBT CLEA R R I R R 0' R2 R, NONDESTRUCTIYE o 0 READOUT REGISTER o v 42 2 RESTORE HG 6 T0 OUTPUT UTILITY cmcuns F SERIAL INPUT 5O SERIAL ADDER CLOCKK MAGNETIC I MAGNETICSHIFT CIRCU PULSES DRUM L58 :wp REGISTER 4 MEMORY AUGEND f @SBRIAL. 48 Y SERIAL READOUT READ m ADDEND c0 puTER MULIIPLY comm.

mowoesmucnvs INVENTORS READOUT REGISTER DAVID LOEV WILLIAM MIEHLE 54 JOSEPH WYLEN msmucnous PAR'QLLEL BY 9 Mum LICATION M 38% SERIAL MULTIPLIER INPUT C'RCUIT ATTORNEY 'gle element. into a specified circuit by establishing current flow in a transfer loop in response to a transfer signal but not in response to a change of storage state alone, is disclosed States 7 2,943,301 MAGNETIC SHIFT REGISTER DavidLoev, Plymouth Meeting, William Miehle, Haverv.town, and Joseph Wylen, Broomall, Pa., assignors to Burroughs Corporation, Detroit, Mich., a corporation of Michigan,

Continuation of application Ser. No. 425,013, Apr. 22, 1954.- This application Sept. 10,1957, Ser. No.

Claims. (Cl. 340174) This application is a continuation of our co-pending application, Serial No. 425,013, filed April 22, 1954.

This invention relates to magnetic switching circuits, and more particularly to magnetic shift register circuits.

Magnetic shift registers are well known in the art as evidenced by published articles such as that entitled An' Electronic Digital Computer published in Electronic Engineering, December 1950 by A, D. Booth. In general, the static magnetic elements, of which the shift register is comprised, have core materials. which display substantiallyrectangular hysteresis characteristics. These we 0 f Patented June 28, 1960 ice gating circuit, but it imposed an additional load upon the shift register advancing. circuits when the register was cores tend to remain in a permanent magnetic remanence condition after being driven into magnetic saturation by signals presented at a transformer winding. The two states of magnetic remanence provided by these cores enable them to efiiciently store binary information and retainit statically until required. When an element is in one remanence condition, little voltage will be induced in the windings about the transformer by input signals of a polarity tending to establish the same remanence condition in the element. However, when themput signal is opposite in polarity to .the storage state within the element, a high voltage is induced and an output signal is afforded by the element. Therefore, when theelements are interrogated with a signal of known polarity, the remanence condition may be determined.

When magnetic elements have a plurality of windings about the core material, then a potential is induced in all of the windings at the time an interrogation signal is applied. Therefore, prior art devices have had to provide asymmetrical circuits or timed gating circuits for distinguishing between desired and undesired output conditions. In addition, the information could'be read out of the cores into'several circuits at the same time, but not selectively into separate specified circuits coupled to only part of the output windings about asin- Means for effecting a conditional trans-fer and claimed in the copending application for' Letters Patent of'John O. Paivinen, Serial No. 762,863, filed September 23, 1958, as a continuation of three earlierfilcd Paivinen applications, Serial Nos. 396,603 and 396,605; filed December 7, 1953, and Serial No. 420,- 135, fild March 31, 1954, thelast being a continuationin-part of Paivinen application SerialNo. 396,604, ffiled December 7, 1953, each of said Paivinen applications being assigned to the assignee of the present application.

either a portion of a'shift register circuit or from the entire register. In addition, it has not been convenient to being filled because current was excited in the read-out windings as well as the shift register windings.

It is, therefore, a general object of the invention to improve electronic switching and shift register circuits of the prior art." r

It is'another object of the invention toprovide improved conditional transfer circuits tor magnetic shift register systems.

A further object of the invention is to provide eflicient serial'input-parallel output shiftregisterapparatus.'

A still further object of the invention is to provide means for conditionally. clearing or erasing a partor all of the information stored ina magneticlshifttregister.

In accordance with one embodiment of th'e present invention, therefore, there is provided a conditional transfer network or loop for selectively reading information out of a staticmagnetic element-into different transfer'paths V element into the transferee element. With-unidirectional devices in each branch path, current can be blocked whenever a change of remanence condition occurs'in the transferor element during 'a period when-the. en-

abling current how is absent.

' By-connecting a shift registercircuit with? cascade,

coupled conditional transfer. networks of this type; in} formation may be advanced serially in rsponse tota first source of shifting signals. In those transferor'reister elements from which information is to be read or erased, a second conditional transfer network or loop of the same type is coupled to a circuit external to the register for actuation by aseparate source of'shifting signals.

tailed description of the invention and its organization. These features illustrating theinventiofi may-be more This action tendsto cause a transfer of the stored information from the. transferor Therefore, the registers may be clearediwithout shifting the information to another position within a) readily understood when considered in connection with the accompanying drawings, in which:

Figs. 1, 2A, 2B, and 3 are schematic circuit diagrams of magnetic shift registers of the invention employing different conditional transfer loop modifications.

Fig. 4 is a logical circuit diagram of conditional transfer shift register circuits constructed in accordance with the invention; 9 1 f r Fig. 5-is a logical block diagram of a non-destructive serial input-parallel read-out register system constructed in accordance with the invention; and I Fig. 6 is a block diagram of a portion of a digital computer arithmetic system incorporating means pro? vided by the present invention.

Those features whose details are not of themselves a part of the invention, and which are well known in the art,- are shown in block diagram form so that the features of the present invention may be more readily recognized. Throughout the drawings, like reference characters are used to designate similar elements in order to facilitate comparison of the several views.

A typical magnetic shift register constructed in accordance with the present invention is shown schematically in Fig. 1. Four magnetic elements 12 to 15 are shown connected in a conventional magneticshift register circuit with an input circuit at which binary information may be entered serially into the first magnetic element 12. The magnetic core is shown schematically to have a core of such material that binary magnetic storage of the digits 1 or 0 may be excited by appropriate input signals. The notation at each of the input windings determines which of the states will be established in the' element by signals from a circuit connected to the winding. Thus, information'at the input winding 10 establishes a -1 state in the element 12. Conversely, the output winding notation signifies that a signal will be generated when. the core is returned from an opposite state to that indicated.

The stored information is progressively transferred from element to element along the cascade coupled elements 13, 14 and 15 in response to alternate signals at the respective shift terminals or and ,6. The register oomprises alternate sets ofstorage sub-registers designated as elements A and B, wherein the elements B comprise a sub-register for temporary storage of the information 'in transit from one of the A elements to the next. This is necessarysince the information must be removed from one element by reset to a predetermined condition before further information may be entered.

Up to this point the described shift register circuit is conventional. However, with such conventional techniques it is not feasible to efficiently provide parallel read-out signals from the elements in one sub-register such as A. With a conventional circuit, for example, in which a stored binary digit 1 is read out of element 12 by a shift a signal returning the element to its 0 4. ance is maintained the net flux established is essentially zero and therefore no storage is effected. However, with unbalanced currents, one or the other of the storage states may be established.

Unbalanced currents in the conditional transfer circuit may be established by connecting a read-out winding in only one of the balanced branch current paths so that unbalance is caused only when a signal is stored and read out. Thus, when a T signal reads out a stored 1 from element 12, the current flow in the parallel readout winding 19 will cause a larger current to flow in the lower half of winding 21 of the transfer loop than in the upper half of the windingand therefore, will store the l"- in element 23. However, balance is substantially maintained when a 0 is stored in element 12 and the 0 is retained in element 23. If the read-out winding 19 has a large number of turns, say one hun state, a read-out signal current is provided not only in the register winding 17 but also in the parallel read-out winding 19. Therefore, a signal is simultaneously read out into two circuits, and the interrogation signal or must supply enough switching energy to eifect this operation.

In addition, some type of selectively actuating gating circuits must be provided to prevent the signals read out from entering the read-out register elements R at,

tap, two branch current flow paths setting up opposing n agnetic fields the read-out element 23. When bal- .sists of a transformer winding having a center tap so .that; an input signal will establish, relative to the center dred, as-compared' with the turns, such as five, of half the split winding 21, the smaller unbalanced current due to the high impedance of winding 19 during transfer will cause read-out of the information in element 12 by a return of the remanence state to 0,? thereby shifting the information to element 13 by way of the conventional unconditional shift register transfer loop.

In this embodiment, therefore, the shift register is not cleared but the information is shifted one place along the register and is there retained for further use, if desired. With a shift operation in response to an an interrogation signal at element 12, the voltage induced in readout winding 19 cannot cause current flow inthe conditional transfer loop because of the current blocking rectifiers 16;. Thus, the information'is only transferred into element 13 and, is not gated into element 23. It is clear that when the shift operation is performed no transfer of the stored information is effected into the read-out element 23. Accordingly, the presently described circuit not only provides more eflicient operation, and a selective gating of the parallel read-out signal when desired, but in addition, affords means for obtaining non-destructive read-out of a shift circuit.

Read-out of the information in element 23 is effected by conventional means such as establishing a 0" state in the element with read-out winding 25 thereby providing an output signal 13. at output winding 27. The signal E appearing at the output winding 27 is provided only at the time the element. is switched from a ,1 condition to a 0 condition because of the asymmetriflal rectifier device in series with the winding. This rectifier is optional and need not be used where the output circuit itself is discriminatory to the switching direction, or where output signals in response to switching in both directions are not undesirable. Either input condition l or- 0 may be established in a given element by properly choosing the direction of current flow through the input or read-out windings 10 or 25 respectively.

Another conditional transfer shift register embodiment of this invention is shown in Fig. 2A. In this embodiment conditional transfer loops are used both to afford cascade coupling along the elements of the shift register and from elements A of the shift register to the corresponding elements R of a read-out register. If a single read-out element 23 is employed, the circuit parameters many be chosen to selectively erase the information from in response to an erase pulse may flow through the transfer winding 19 and reset element 12 to Q at the same time that element 23' is switched, to a 1 storage state by currentv flow throughthe lower half of the split winding 21.

Several different modes of coupling this type of conditional transfer circuit are shown in the respective transfer loops 32 and 33. In the transfer loop 32 the asym metrical diodes and resistors are coupled in series with one lead connecting the ends of the respective read-out and balanced winding circuits. The operation of this circuit is equivalent to the operation of the transfer loop 33 where the resistors and diodes are connected respectively in each of the leads coupling the read-out and balanced winding circuits; The resistors are employed as a precautionary measure to assure a balanced current flow condition in the balanced winding circuit even though small circuit variations or differences of a few turns in one of the windings might otherwise cause a small unbalance. In addition, the resistance of output winding 17 in one currnet branch may be compensated for by resistor 18 in the other branch, ifdesired. Operation of the circuit may be effected without the resistors, if desired, and in this case the split winding 21 of the transfer loop 33 may be unbalanced for compensation if necessary. In addition, the shifting or advancing pulses a and ,3 may be applied serially through several windings as shown in Fig. 1, or in parallel to all of the windings as implied in Fig. 2A., With the conditional transfer circuits herein described, operation of magnetic storage elements of this type is made extremely flexible and reliable. 1

In Fig. 2B the read-out or advancing winding 20 upon the B shift register element 15' is isolated from the transfer loops 36 and 36'. Thus, a transfer of the information of either binary state residing in element 15' is effected if current is flowing in the transfer loops 36 and/or 36' fat the time the core is switched. With the element 15 in a static state the current i will flow equally in each half of the balanced winding circuits of transfer loops 36 and 36 thereby affording opposing flux which will not disturb the stored information. However, if switching takes place in the element 15' a potential will be induced acrossthe entire split winding 22 or 22'of each transfer loop 36 and 36, which will aid current flow in one half and oppose current flow in the other half. The direction of current fiow in the transferee element windings 24 or 24 will depend upon the direction of the switching, and therefore information 'of either binary state may be transferred from element. 15. To effect conditional transfer at any time to either'read-out element 26 or register element 23, the current in the transfer loops 36 and 36 may be gated. x

A further alternative circuit connection is shown in Fig. 3 wherein split windings are employed on both the transferor and transferee elements .of the transfer loops 35. In this case, an unbalancing winding 39 is employed on the transferor element for causing unbalanced current flow in the branchedpaths of transfer loops 35 only in response to-selectively appliedshifting or advancing currents oz, d or T occurring with a. change in the remanence state, and not in response .to the mere change of remanence state of the cores. The respective shifting currents at and [3 in this embodiment are coupled serially through those windings connected by leads identified Soc and S3. The 00 notation at the transferorwinding 19 indicates that an output signal is effected when the element is changed, from a I to a 0 condition by current flowing in the winding 39. In considering the B sub-register elements,'from which 'a parallel transfer is effected, it is seen that the eyebrow connection lines between the respective Os of the balanced winding circuits indicate'the condition which must be established to effect transfer of information uniquely in one or the other of io iiaoi to aid and the other half to oppose the current flow;

Therefore there will be .one branch in which the'jcurr'ent may pass more readily than the other during the switch ing period, which results in transferring the stord'information to the succeeding element. Several different embodiments or modifications of the conditional transfer circuits have been shown in order to enable those skilled in the art to adapt the present invention to any particular system application. It is, however, clear that further embodiments may be employed without departing from the spirit or scope of the present invention. 1

In order to simplify 'the logical presentation of the conditional transfer circuits hereinbefore described, a logical diagram notation of a conditional transfer shift register circuit has been derived as shown in Fig. 4.- The static magnetic elements are shown as circles at which input arrows represent windings to which input signals are presented. The designation of either a 0 or a l at the end of the input arrows represents the condition to which the element is switched 'or retained when a signal is present. Conversely, output windings are represented by lines leaving the elements, and the notation determines the condition to which the elements must be switched from the opposite condition in order to provide output signals. The eyebrow notation such as between the desig nation of input and output windings 19 and 39, is used generically to denote the conditional transfer type circuits shown and described in Figs. 1, 2A, 2B, and 3;; The I block diagram of Fig. 4jtherefore-corresponds to the circuit, and the information in the register is shifted to To free.

a new position in the register upon read-out. the shift register for. receiving new information while the information which has been read out in parallel is used non-destructively, the non-destructive read-out register generally indicated at 40 in Fig. 5 is employed. Such a non-destructive. read-out register is described and claimed in copending application of William Miehle (one of the joint inventors of the present application), Serial No. 791,002, filed January 30, 1959; as a continuation of his earlier application Serial No. 407,120, filed January 29, 19 54, and assigned to the assignee of the present application. This register utilizes the conditional transfer circuits hereinbefore described. As information is read out of the serial input register in parallel from the sub-register elements .13, it is stored in the noning signals from a serial shift register circuit to a parallel read-out circuit by means of the present invention.

The non-destructive read-out register is also provided internally with conditional transfer circuits which-may be excited by the respective -R R etc. read-out pulses. ,As one of these respective read-out pulses is provided at any one of the R cores such as 23', the information is transferred to the associated element 45 in the lower group of elements of the read-ou t register 40. At the assessor time of transfer into element 45 an output signal may be provided to suitable output utility circuits, if desired. In this manner, all the R R etc. leads may be pulsed in parallel for parallel utilization of the information therein, or conversely they may be pulsed in any order orfsequence in order to partially use the information or to use it in sequence. By means of a conventional shift winding, the information is restored into the upper ele ments by restore commands at terminal 42. Clearing this register may be done by the simple expedient of passing current through a conventional winding on the upper read-out register elements R R etc. Clear pulses at terminal 43 change the states of the cores with: out reading the information out because of the conditional transfer circuits within register 40. The clearing operation is thus accomplished much more simply and endciently, since less power is required than when inhibit pulses are additionally used to prevent the entering of information in the lower read-out register elements at the same time that it is cleared from the upper elements R. The clearing operation should be performed in time sequence with the restoring operation in order to assure that all the stored information is returned to register elements R for clearing.

Serial input-parallel output registers of the type described are highly useful in arithmetic units of electronic computers, such as that shown by block diagram in Fig. 6. In an arithmetic unit designed for serial addition, it is desirable to afford parallel multiplication when attempting to keep the elapsed time for each arithmetic operation as constant as possible. Should the multiplication be effected in serial, many operations would be required and the multiplication time would be much longer than the addition time. Therefore, the serial input magnetic shift register 48 is provided for serial output into an adder circuit 50. However, for multiplication, parallel read out is provided into the non-destructive read-out register 52, which is used to selectively excite the parallel multiplication circuit 54 in response to multiplication instructions emanating from the computer control circuits 56. Input signals may be taken from a memory storage device such as a magnetic drum 58 from which timing or clock pulses are derived in order to effect operation in the proper time relationship. Wherever the clock pulses are used to effect timing of a particular operation, logical "and circuits are inserted which require both a command signal and a clock signal for passing information. The organization of this type of computer circuit is well known in the art, and the details of the computer arrangement itself are not part of the present invention. The diagram, however, typifies apparatus in which the circuits of the present invention are advantageously employed.

Having therefore described the invention and its organization, it is requested that Letters Patent be granted on the appended claims, which are believed descriptive of those novel features contributed to advance the state of the art,

What is claimed is:

l. A magnetic storage system comprising a magnetic shift register including a plurality of magnetic storage elements. electrical circuitry interconnecting successive storage elements of the shift register for transferring information from element to element therealong, and separate electrical circuitry coupled to the last storage element of the shift register for interconnecting said element to a load; first transfer means within the register for advancing information serially from element to element'in response to a signal from a first source; a transfor loop coupled to the register for conditionally readmg, in response to a signal from a second source, information out of at least onetransferor element of the register and into a transferee circuit external of said shift register, said transferee circuit having at least one transferee element, said transfer loop coupling said transferor element and said transferee element and comprising a pair of substantially balanced branched current llow paths for receiving a flow of current from said second signal source for providing a net flux of sufiicient magnitude in said transferee element in response to said currentflow only upon dynamic switching of the transferor element to cause switching of the transferee element; and means in said transfer loop for preventing current flow through said loop in response to a change of flux in said transferor element in the absence of a signal from said second source. 2. A system as defined in claim 1 wherein the pair of branched current flow paths includes on each the trans feror element and the transferee element one portion of a winding having a mid-tap, and a read-out winding on the transferor element serially connected with said midtap to receive the total current flowing in the branch circuits.

3. In combination; a binary register adapted for seriesinput parallel-output operation and comprising a plurality of bistable elements coupled in cascade formation, input means for inserting binary data into said register, and shift means for shifting said data through said register in step-by-step manner; a plurality of bistable output elements; and a conditional transfer loop coupling each of said output elements to a different one of said register elements, each of said conditional transfer loops including: an output winding associated with said register element, a center-tapped input winding associated with said output element, a pair of asymmetrically conducting devices poled to inhibit current flow around said loop, and means for connecting a source of pulse current between the center-tap on said input winding and a point on said loop located between said asymmetrically-conductingdevices, thereby to establish parallel current-flow paths between said register element and output element, said asymmetrically-conducting devices operating to inhibit transfer of data from said register element to said output element. in the absence of said pulse current, whereby data may be inserted serially into and shifted through said register without developing signals in said output elements, and whereby said register data may be transferred from selected register elements to associated output elements in response to the application of a pulse of current to the conditional transfer loop coupled therebetween.

4. In combination; a shift register comprising: a plurality of magnetic cores each capable of assuming either of two stable states of magnetic remanence, an input output core having a tap at its mid-point, a pair of diodes poled to inhibit current flow around the transfer loop, and means for connecting a source of enabling pulse current between said input-winding tap and a point on said loop located between said diodes, thereby to establish parallel current-flow paths between the register core and the associated output core, whereby data stored in the register core is transferred to the output core by way of one of said parallel current-flow paths and only in the presence of said enabling pulse current.

5. Apparatus as claimed in claim 4 characterized in that the said transfer loops which couple the cores of the shift register in cascade formation are likewise conditional transfer loops and include an output winding on one register core, a mid-tapped input winding on the next register core, and a pair of diodes poled to inhibit current flow around the register transfer loop; and in that the said shift-current means includes means for connecting a second source of enabling pulse current between the said mid-tap point on said register-core input winding and a point on said register transfer loop located between said last-named diodes, thereby to establish parallel currentflow paths between the said one register core and the said next register core, whereby data stored in the, said one register core is transferable to the said next register core by way of one of said parallel current-flow paths and only in the presence of a pulse of enabling current from said second source.

References Cited in the file of this patent UNITED STATES PATENTS Karnaugh Oct. 4, 1955 Saunders Nov. 6, 1956 Browne Apr. 29, 1958 FOREIGN PATENTS Great Britain Feb. 13, 1957 

